MC68HC05RC8 Datasheet, PDF (49/122 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Resets
Internal Resets
5.5.2 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU.
The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
5.5.2.1 Resetting the COP
Writing a zero to the COPF bit prevents a COP reset. This action resets
the counter and begins the time-out period again. The COPF bit is bit 0
of address $3FF0. A read of address $3FF0 returns user data
programmed at that location.
5.5.2.2 COP During Wait Mode
The COP continues to operate normally during wait mode. The software
should pull the device out of wait mode periodically and reset the COP
by writing to the COPF bit to prevent a COP reset.
5.5.2.3 COP During Stop Mode
When the stop enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device.
When stop is executed, the COP counter will hold its current state. If a
reset is used to exit stop mode, the COP counter is reset and held until
4064 POR cycles are completed at this time, counting will begin. If an
external IRQ is used to exit stop mode, the COP counter does not wait
for the completion of the 4064 POR cycles but does count these cycles.
It is, therefore, recommended that the COP is fed before executing the
STOP instruction.
MC68HC05RC16 — Rev. 3.0
General Release Specification
Resets
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