MSC8254_11 Datasheet, PDF (56/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor

Hardware Design Considerations
2. After the above rails rise to 90% of their nominal voltage, the following I/O power rails may rise in any sequence (see
Figure 34): QVDD, NVDD, GVDD1, and GVDD2.
NVDD, QVDD, GVDD1, GVDD2
90%
VDD, MVDD, M3VDD
Figure 34. Supply Ramp-Up Sequence
Notes: 1. If the M3 memory is not used, M3VDD can be tied to GND.
2. If the HSSI port1 is not used, SXCVDD1and SXPVDD1 must be connected to the designated power supplies.
3. If the HSSI port2 is not used, SXCVDD2 and SXPVDD2 must be connected to the designated power supplies.
4. If the DDR port 1 interface is not used, it is recommended that GVDD1 be left unconnected.
5. If the DDR port 2 interface is not used, it is recommended that GVDD2 be left unconnected.
3.1.4 Reset Guidelines
When a debugger is not used, implement the connection scheme shown in Figure 35.
On-board PORESET source
(example: voltage monitor)
MSC815x
TRST
PORESET
Figure 35. Reset Connection in Functional Application
When a debugger is used, implement the connection scheme shown in Figure 36.
VDD_IO
On-board TRST source
(example: OnCE)
10 ΚΩ
MSC815x
On-board PORESET source
(example: voltage monitor)
TRST
PORESET
Figure 36. Reset Connection in Debugger Application
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 6
56
Freescale Semiconductor