MSC8254_11 Datasheet, PDF (34/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor

Electrical Characteristics
Table 14. Serial RapidIO Receiver DC Specifications
Parameter
Symbol
Min
Typical
Max
Differential input voltage
Notes: 1. Measured at receiver.
V_IN
200
—
1600
Units
mVp-p
Notes
1
2.5.3.4 DC-Level Requirements for SGMII Configurations
Note: Specifications are valid at the recommended operating conditions listed in Table 3
Table 15 describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are
measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) as shown in Figure 10.
Table 15. SGMII DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit Notes
Output high voltage
Output low voltage
Output differential
voltage (XV_DD-Typ at
1.0 V)
V_OH
V_OL
|V_OD|
—
—
XV_{DD_SRDS-Typ}/2 + |V_OD|_-max/2
mV
XV_{DD_SRDS-Typ}/2 – |V_OD|_-max/2
—
—
mV
323
500
725
mV
296
459
665
269
417
604
1
1
2,3,4
2,3,5
2,3,6
243
376
545
2,3,7
215
333
483
2,3,8
189
292
424
2,3,9
Output impedance
R_O
(single-ended)
162
250
362
40
50
60
2,3,10
Ω
—
Notes:
1. This does not align to DC-coupled SGMII. XV_{DD_SRDS2-Typ} = 1.1 V.
2. The |V_OD| value shown in the table assumes full multitude by setting srd_smit_lvl as 000 and the following transmit
equalization setting in the XMITEQAB (for lanes A and B) or XMITEQEF (for lanes E and F) bit field of Control Register:
• The MSB (bit 0) of the above bit field is set to zero (selecting the full V_DD-DIFF-p-p amplitude which is power up default);
• The LSB (bit [1–3]) of the above bit field is set based on the equalization settings listed in notes 4 through 10.
3. The |V_OD| value shown in the Typ column is based on the condition of XV_{DD_SRDS2-Typ} = 1.0 V, no common mode offset
variation (V_OS =500mV), SerDes transmitter is terminated with 100-Ω differential load between
4. Equalization setting: 1.0x: 0000.
5. Equalization setting: 1.09x: 1000.
6. Equalization setting: 1.2x: 0100.
7. Equalization setting: 1.33x: 1100.
8. Equalization setting: 1.5x: 0010.
9. Equalization setting: 1.71x: 1010.
10. Equalization setting: 2.0x: 0110.
11. |V_OD| = |V_{SR[1–2]_TXn}– V_{SR[1–2]_TXn}|. |V_OD| is also referred to as output differential peak voltage. V_TX-DIFFp-p = 2*|V_OD|_.
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 6
34
Freescale Semiconductor