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MSC8254_11 Datasheet, PDF (50/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor | |||
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Electrical Characteristics
2.6.6 SPI Timing
Table 36 lists the SPI input and output AC timing specifications.
Table 36. SPI AC Timing Specifications
Parameter
Symbol 1
Min
Max
Unit
Note
SPI outputs validâMaster mode (internal clock) delay
tNIKHOV
â
6
ns
2
SPI outputs holdâMaster mode (internal clock) delay
tNIKHOX
0.5
â
ns
2
SPI outputs validâSlave mode (external clock) delay
tNEKHOV
â
12
ns
2
SPI outputs holdâSlave mode (external clock) delay
tNEKHOX
2
â
ns
2
SPI inputsâMaster mode (internal clock) input setup time
tNIIVKH
12
â
ns
â
SPI inputsâMaster mode (internal clock) input hold time
tNIIXKH
0
â
ns
â
SPI inputsâSlave mode (external clock) input setup time
tNEIVKH
4
â
ns
â
SPI inputsâSlave mode (external clock) input hold time
tNEIXKH
2
â
ns
â
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until
outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal.
Timings are measured at the pin.
Figure 26 provides the AC test load for the SPI.
Output
Z0 = 50 Ω
RL = 50 Ω
VDDIO/2
Figure 26. SPI AC Test Load
Figure 27 and Figure 28 represent the AC timings from Table 36. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 27 shows the SPI timings in slave mode (external clock).
SPICLK (input)
Input Signals:
SPIMOSI
(See note)
Output Signals:
SPIMISO
(See note)
tNEIVKH
tNEIXKH
tNEKHOV
Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
Figure 27. SPI AC Timing in Slave Mode (External Clock)
Figure 28 shows the SPI timings in master mode (internal clock).
tNEKHOX
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 6
50
Freescale Semiconductor
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