MSC8254_11 Datasheet, PDF (3/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor

JTAG
DDR Interface 64/32-bit
DDR
Controller
CLASS
SC3850
DSP Core
32 Kbyte 32 Kbyte
L1
L1
ICache DCache
512 Kbyte
L2 Cache / M2 Memory
Four DSP Cores at 1 GHz or 800 MHz
Four TDMs 256-Channels each
Note: The arrow direction indicates master or slave.
DDR Interface 64/32-bit
DDR
M3 Memory
Controller 1056 Kbyte
QUICCEngine
Subsystem
Dual RISC Processors
SPI Ethernet Ethernet
High-Speed Serial Interface
DMA
DMA
RMU ^{Serial Serial PCI}
RapidIO RapidIO Expr
SGMII
x2
SerDes 1 SerDes 2
I/O-Interrupt
Concentrator
UART
Clocks
Timers
Reset
Semaphores
Virtual
Interrupts
Boot ROM
I²C
Other
Modules
SPI RGMII RGMII
4x 3.125 Gbaud
PCI-EX 1x/2x/4x
Two SGMII
4x 3.125 Gbaud
Two SGMII
Figure 1. MSC8254 Block Diagram
128 bits master
bus to CLASS
128 bits slave
bus from CLASS
Interrupts
TWB
512 Kbyte L2 Cache / M2 Memory
IQBus
DQBus
EPIC
Debug Support
OCE30 DPU
SC3850
Core
32 Kbyte
Instruction
Cache
Write-
Through
Buffer
(WTB)
32 Kbyte
Data
Cache
Write-
Back
Buffer
(WBB)
P-bus 128 bit
Xa-bus 64 bit
Xb-bus 64-bit
Timer
Task
Protection
Address
Translation
MMU
Figure 2. StarCore SC3850 DSP Subsystem Block Diagram
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
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