MSC8254_11 Datasheet, PDF (33/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor

Electrical Characteristics
Note: Specifications are valid at the recommended operating conditions listed in Table 3.
Table 11. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential peak-to-peak output voltage
V_TX-DIFFp-p
800
1000
1200
mV
1
De-emphasized differential output voltage (ratio) V_TX-DE-RATIO
3.0
3.5
4.0
dB
2
DC differential Tx impedance
Z_TX-DIFF-DC
80
100
120
Ω
3
Transmitter DC impedance
Z_TX-DC
40
50
60
Ω
4
Notes: 1. V_TX-DIFFp-p = 2 × |V_TX-D+ – V_TX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Ratio of the V_TX-DIFFp-p of the second and following bits after a transition divided by the V_TX-DIFFp-p of the first bit after a
transition. Measured at the package pins with a test load of 50 Ω to GND on each pin.
3. Tx DC differential mode low impedance
4. Required Tx D+ as well as D– DC Impedance during all states
Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input peak-to-peak voltage
V_RX-DIFFp-p
120
1000
1200
mV
1
DC differential Input Impedance
Z_RX-DIFF-DC
80
100
120
Ω
2
DC input impedance
Z_RX-DC
40
50
60
Ω
3
Powered down DC input impedance
Z_{RX-HIGH-IMP-DC}
50
—
—
ΚΩ
4
Electrical idle detect threshold
V_{RX-IDLE-DET-DIFFp-p}
65
—
175
mV
5
Notes: 1. V_RX-DIFFp-p = 2 × |V_RX-D+ – V_RX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to
detect (the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all
unconfigured lanes of a port.
3. Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50 Ω to
GND on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state
of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of
a port.
4. Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode
impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect
circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx
ground.
5. V_{RX-IDLE-DET-DIFFp-p} = 2 × |V_RX-D+ – V_RX-D–|. Measured at the package pins of the receiver
2.5.3.3 DC-Level Requirements for Serial RapidIO Configurations
This sections provided various DC-level requirements for Serial RapidIO Configurations.
Note: Specifications are valid at the recommended operating conditions listed in Table 3.
Table 13. Serial RapidIO Transmitter DC Specifications
Parameter
Symbol
Min
Output voltage
V_O
–0.40
Long run differential output voltage
V_DIFFPP
800
Short run differential output voltage
V_DIFFPP
500
Note: Voltage relative to COMMON of either signal comprising a differential pair.
Typical
—
—
—
Max
2.30
1600
1000
Units
V
mVp-p
mVp-p
Notes
1
—
—
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
33