MSC8254_11 Datasheet, PDF (38/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor

Electrical Characteristics
Figure 11 shows the DDR2 and DDR3 SDRAM interface input timing diagram.
MCK[n]
MCK[n]
t_MCK
MDQS[n]
MDQ[n]
t_DISKEW
t_DISKEW
D0
D1
t_DISKEW
Figure 11. DDR2 and DDR3 SDRAM Interface Input Timing Diagram
2.6.1.2 DDR SDRAM Output AC Timing Specifications
Table 21 provides the output AC timing specifications for the DDR SDRAM interface.
Table 21. DDR SDRAM Output AC Timing Specifications
Parameter
MCK[n] cycle time
ADDR/CMD output setup with respect to MCK
• 800 MHz data rate
• 667 MHz data rate
ADDR/CMD output hold with respect to MCK
• 800 MHz data rate
• 667 MHz data rate
MCSn output setup with respect to MCK
• 800 MHz data rate
• 667 MHz data rate
MCSn output hold with respect to MCK
• 800 MHz data rate
• 667 MHz data rate
MCK to MDQS Skew
• 800 MHz data rate
• 667 MHz data rate
MDQ/MECC/MDM output setup with respect to MDQS
• 800 MHz
• 667 MHz
MDQ/MECC/MDM output hold with respect to MDQS
• 800 MHz
• 667 MHz
MDQS preamble
MDQS postamble
Symbol ¹
t_MCK
t_DDKHAS
t_DDKHAX
t_DDKHCS
t_DDKHCX
t_DDKHMH
t_DDKHDS,
t_DDKLDS
t_DDKHDX,
t_DDKLDX
t_DDKHMP
t_DDKHME
Min
2.5
0.917
1.10
0.767
1.02
0.917
1.10
0.767
1.02
–0.4
–0.6
300
375
300
375
–0.9 × t_MCK
–0.4 × t_MCK
Max
5
—
—
—
—
—
—
—
—
0.375
0.6
—
—
—
—
—
–0.6 × t_MCK
Unit Notes
ns
2
3
ns
ns
3
ns
ns
3
ns
ns
3
ns
ns
ns
4
5
ps
ps
5
ps
ps
ns
—
ns
—
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 6
38
Freescale Semiconductor