MC68331CEH16 Datasheet, PDF (52/84 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
Table 22 QSM Address Map
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Address
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
$YFFC20–
$YFFCFF
$YFFD00–
$YFFD1F
$YFFD20–
$YFFD3F
$YFFD40–
$YFFD4F
15
87
0
QSM MODULE CONFIGURATION (QSMCR)
QSM TEST (QTEST)
QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)
NOT USED
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SCI STATUS (SCSR)
SCI DATA (SCDR)
NOT USED
NOT USED
NOT USED
PQS DATA (PORTQS)
PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
SPI CONTROL 3 (SPCR3)
SPI STATUS (SPSR)
NOT USED
RECEIVE RAM (RR[0:F])
TRANSMIT RAM (TR[0:F])
COMMAND RAM (CR[0:F])
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR
5.2 Pin Function
The following table is a summary of the functions of the QSM pins when they are not configured for gen-
eral-purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an in-
put or output.
QSPI Pins
SCI Pins
Pin
MISO
MOSI
SCK
PCS0/SSMaster
PCS[3:1]
TXD
RXD
Mode
Master
Slave
Master
Slave
Master
Slave
Slave
Master
Slave
Transmit
Receive
Pin Function
Serial Data Input to QSPI
Serial Data Output from QSPI
Serial Data Output from QSPI
Serial Data Input to QSPI
Clock Output from QSPI
Clock Input to QSPI
Input: Assertion Causes Mode Fault
Output: Selects Peripherals
Input: Selects the QSPI
Output: Selects Peripherals
None
Serial Data Output from SCI
Serial Data Input to SCI
52
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