MC68331CEH16 Datasheet, PDF (22/84 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
2
22 pF
V_SSI
32.768 KHz
R4
330K
R3
10M
2
22 pF
V_SSI
EXTAL
XTAL
CRYSTAL
OSCILLATOR
PHASE
COMPARATOR
1
XFC
V _DDSYN
0.1µF
0.1µF
0.01µF
XFC PIN
VDDSYN
V_SSI
LOW-PASS
FILTER
VCO
W
FEEDBACK DIVIDER
Y
X
SYSTEM CLOCK CONTROL
SYSTEM
CLOCK
CLKOUT
1. MUST BE LOW-LEAKAGE CAPACITOR (INSULATION RESISTANCE 30,000 MΩ OR GREATER).
2. RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL. _{SYS CLOCK}
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
BLOCK 32KHZ
Figure 7 System Clock Block Diagram
3.3.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines the clock source. When MODCLK
is held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator
or an external reference input. Clock synthesizer control register SYNCR determines operating frequen-
cy and various modes of operation. When MODCLK is held low during reset, the clock synthesizer is
disabled, and an external system clock signal must be applied. When the synthesizer is disabled, SYN-
CR control bits have no effect.
A reference crystal must be connected between the EXTAL and XTAL pins to use the internal oscillator.
Use of a 32.768-kHz crystal is recommended. These crystals are inexpensive and readily available. If
an external reference signal or an external system clock signal is applied through the EXTAL pin, the
XTAL pin must be left floating. External reference signal frequency must be less than or equal to max-
imum specified reference frequency. External system clock signal frequency must be less than or equal
to maximum specified system clock frequency.
When an external system clock signal is applied (i.e., the PLL is not used), duty cycle of the input is
critical, especially at near maximum operating frequencies. The relationship between clock signal duty
cycle and clock signal period is expressed:
Minimum external clock period =
minimum external clock high/low time
50% — percentage variation of external clock input duty cycle
22
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MC68331TS/D
Go to: www.freescale.com