MC68331CEH16 Datasheet, PDF (33/84 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
Byte
00
01
10
11
Description
Disable
Lower Byte
Upper Byte
Both Bytes
R/W —Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
Refer to the following table for options available.
R/W
Description
00
Reserved
01
Read Only
10
Write Only
11
Read/Write
STRB —Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip select to be asserted synchronized with data strobe.
DSACK —Data and Size Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to op-
timize bus speed in a particular application. The following table shows the DSACK field encoding. The
fast termination encoding (1110) is used for two-cycle access to external memory.
DSACK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
No Wait States
1 Wait State
2 Wait States
3 Wait States
4 Wait States
5 Wait States
6 Wait States
7 Wait States
8 Wait States
9 Wait States
10 Wait States
11 Wait States
12 Wait States
13 Wait States
Fast Termination
External DSACK
MC68331TS/D
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