MC68331CEH16 Datasheet, PDF (19/84 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
SWP —Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] —Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following ta-
ble gives the ratio for each combination of SWP and SWT bits.
SWP
0
0
0
0
1
1
1
1
SWT
00
01
10
11
00
01
10
11
Ratio
2⁹
2¹¹
2¹³
2¹⁵
2¹⁸
2²⁰
2²²
2²⁴
HME —Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME —Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] —Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
BMT
00
01
10
11
Bus Monitor Time-out Period
64 System Clocks
32 System Clocks
16 System Clocks
8 System Clocks
3.2.3 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.2.4 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
MC68331TS/D
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