M68HC11K Datasheet, PDF (51/290 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
CPU Registers
an internal implied subtraction and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY,
and DEY) affect the Z bit and no other condition flags.
3.3.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative, meaning that the most significant bit (MSB) of the
result is a 1. Otherwise, the N bit is cleared. To determine quickly if the
MSB of a particular byte is set, load it into an accumulator and then
check the status of the N bit.
3.3.6.5 Interrupt Mask (I)
When the interrupt mask bit is set, it disables all maskable interrupt
requests (IRQs). The CPU continues to operate uninterrupted while
interrupts remain pending until the I bit is cleared. Every reset sets the
I bit by default and only a software instruction can clear it. When the
processor recognizes an interrupt, it stacks the registers, sets the I bit,
and then fetches the interrupt vector. The final instruction of an interrupt
service routine is usually a return from interrupt (RTI), which restores the
registers to the values that were present before the interrupt occurred
and clears the I bit.
NOTE:
Although the I bit can be cleared earlier in the interrupt service routine,
avoid nesting interrupts in this way without a clear understanding of
latency and of the arbitration mechanism.
Refer to Section 5. Resets and Interrupts.
3.3.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the
arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise,
the H bit is cleared. Half carry is used during binary-coded decimal
(BCD) operations.
M68HC11K Family
MOTOROLA
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
51