M68HC11K Datasheet, PDF (239/290 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Memory Expansion and Chip Selects
Chip Selects
CSIO
Table 11-4. Chip Select Control Parameter Summary
Enable
Valid
Polarity
Size
Start address
Stretch
IOEN in CSCTL
IOCSA in CSCTL
IOPL in CSCTL
IOSZ in CSCTL
Fixed (see size)
IO1S[A:B] in CSCSTR
1 = enabled, 0 = disabled⁽¹⁾
1 = address valid, 0⁽¹⁾ = E high
1 = active high, 0 = active low⁽¹⁾
1 = 4 K ($1000–$1FFF)
0 = 8 K ($0000–$1FFF)⁽¹⁾
0⁽¹⁾, 1, 2, or 3 E clocks
CSPROG
Enable
Valid
Polarity
PCSEN in CSCTL
Fixed (address valid)
Fixed (active low)
Size
PCSZ[A:B] in CSCTL
Start address
Stretch
Priority
Fixed (see size)
PCS[A:B] in CSCSTR
GCSPR in CSCTL
1 = enabled⁽¹⁾, 0 = disabled
0:0 = 64 K ($0000–$FFFF)⁽¹⁾
0:1 = 32 K ($8000–$FFFF)
1:0 = 16 K ($C000–$FFFF)
1:1 = 8 K ($E000–$FFFF)
0⁽¹⁾, 1, 2, or 3 E clocks
1 = CSGPx above CSPROG
0⁽¹⁾ = CSPROG above CSGPx
CSGP1, Enable
CSGP2 Valid
Polarity
Size
Start address
Stretch
Other
1. Configuration at reset
Set size to 0K to disable
G1AV in GPCS1C
G2AV in GPCS2C
G1POL in GPS1C
G2POL in GPS2C
G1SZ[A:D] in GPCS1C
G1SZ[A:D] in GPCS2C
GPCS1A
GPCS2A
CSCSTR
G1DG2 in GPCS1C
G1DPC in GPCS1C
G2DPC in GPCS2C
MXGS2 in MMSIZ
MXGS1 in MMSIZ
1 = address valid, 0 = E high⁽¹⁾
1 = active high, 0 = active low⁽¹⁾
2 K to 512 K in nine steps
0K = disabled⁽¹⁾ can also follow memory
expansion window 1 or window 2
0⁽¹⁾, 1, 2, or 3 E clocks
Allows CSGP1 and CSGP2 to be logically ORed
and driven out the CSGP2 pin
Allows CSGP1 and CSPROG to be logically
ORed and driven out the CSPROG pin
Allows CSGP2 and CSPROG to be logically
ORed and driven out the CSPROG pin.
Allows CSGP2 to follow either 64 K CPU
addresses or 512K expansion addresses
Allows CSGP1 to follow either 64 K CPU
addresses or 512K expansion addresses
M68HC11K Family
MOTOROLA
Memory Expansion and Chip Selects
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Technical Data
239