M68HC11K Datasheet, PDF (111/290 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
Sources of Resets
5.3.4.1 System Configuration Options Register
The clock monitor function is enabled or disabled by the CME control bit
in the OPTION register (see Figure 5-4). The FCME bit in OPTION
overrides CME and enables the clock monitor until the next reset.
Address: $0030
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ADPU CSEL IRQE
DLY
CME FCME CR1
CR0
Write:
Reset: 0
0
0
1
0
0
0
0
Figure 5-4. System Configuration Options Register (OPTION)
NOTE: In normal operating modes, these bits can be written only once within 64
bus cycles after reset.
CME — Clock Monitor Enable Bit
This control bit can be read or written at any time and controls whether
or not the internal clock monitor circuit triggers a reset sequence when
the system clock is slow or absent. When it is clear, the clock monitor
circuit is disabled. When it is set, the clock monitor circuit is enabled.
Reset clears the CME bit.
0 = Clock monitor disabled
1 = Clock monitor enabled
FCME — Force Clock Monitor Enable Bit
0 = Clock monitor follows the state of the CME bit.
1 = Clock monitor is enabled until the next reset.
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. An E-clock frequency below 10 kHz
generates a clock monitor error. An E-clock frequency of 200 kHz or
more prevents clock monitor errors. Using the clock monitor function
when the E clock is below 200 kHz is not recommended.
M68HC11K Family
MOTOROLA
Resets and Interrupts
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Technical Data
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