M68HC11K Datasheet, PDF (108/290 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
Three registers are involved in COP operation:
• The CONFIG register contains a bit which determines whether the
COP system is enabled or disabled.
• The OPTION register contains two bits which determine the COP
timeout period.
• The COPRST register must be written by software to reset the
watchdog timer.
NOTE:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
5.3.3.1 System Configuration Register
In normal modes, COP is enabled out of reset and does not depend on
software action. To disable the COP system, set the NOCOP bit in the
CONFIG register (see Figure 5-1). In special test and bootstrap
operating modes, the COP system is initially inhibited by the disable
resets (DISR) control bit in the TEST1 register. The DISR bit can
subsequently be written to 0 to enable COP resets.
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ROMAD
1
Write:
CLKX PAREN NOSEC NOCOP ROMON EEON
Reset: —
1
—
—
1
—
—
—
Figure 5-1. System Configuration Register (CONFIG)
NOTE: CONFIG is writable once in normal modes and writable at any time in
special modes.
NOCOP — COP System Disable Bit
0 = COP enabled
1 = COP disabled
Technical Data
108
Resets and Interrupts
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M68HC11K Family
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