M68HC11K Datasheet, PDF (190/290 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Timing System
Freescale Semiconductor, Inc.
PR[1:0] — Timer Prescaler Select Bits
These bits determine the main timer prescale divisor, as shown in
Table 9-2. The system bus (E clock) frequency is divided by this
number to produce the clock which drives the free-running counter.
Refer to Table 9-1 for specific timing values.
In normal modes, PR[1:0] can be written only once, and the write must
be within 64 cycles after reset.
Table 9-2. Timer Prescale
PR[1:0]
00
01
10
11
Prescaler
1
4
8
16
9.4.4 Port A Data Direction Register
Address: $0001
Bit 7
6
5
4
3
2
1
Read:
DDA7
Write:
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
Reset: 0
0
0
0
0
0
0
Figure 9-6. Port A Data Direction Register (DDRA)
Bit 0
DDA0
0
DDA3 — Data Direction Control for Port A, Bit 3
0 = PA3 configured as an input
1 = PA3 configured as an output
Technical Data
190
Timing System
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M68HC11K Family
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