M68HC11K Datasheet, PDF (230/290 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog-to-Digital (A/D) Converter
10.5 Design Considerations
This section discusses design considerations.
10.5.1 A/D Input Pins
Port E pins can also be used as general-purpose digital inputs. Digital
reads of port E pins are not recommended during the sample portion of
an A/D conversion cycle, when the gate signal to the N-channel input is
on. No P-channel devices are directly connected to either input pins or
reference voltage pins, so voltages above V_DD do not cause a latchup
problem, although current should be limited according to maximum
ratings. Refer to Figure 10-6.
ANALOG
INPUT
PIN
< 2 pF
+ ~20 V
– ~0.7 V
INPUT
PROTECTION
DEVICE
+ ~12 V
– ~0.7 V
DUMMY N-CHANNEL
OUTPUT DEVICE
DIFFUSION/POLY
COUPLER
SEE NOTE 1
≤ 4 kΩ
400 nA
JUNCTION
LEAKAGE
*
~ 20 pF
DAC
CAPACITANCE
V_RL
Note 1. This analog switch is closed only during the 12-cycle sample time.
Figure 10-6. Electrical Model of an A/D Input Pin (Sample Mode)
10.5.2 Operation in Stop and Wait Modes
If a conversion sequence is in progress when either the stop or wait
mode is entered, the conversion of the current channel is suspended.
When the MCU resumes normal operation, that channel is resampled
and the conversion sequence is resumed. As the MCU exits the wait
mode, the A/D circuits are stable and valid results can be obtained on
the first conversion. However, in stop mode, all analog bias currents are
disabled and it is necessary to allow a stabilization period when leaving
stop mode. If stop mode is exited with a delay (DLY = 1), there is enough
time for these circuits to stabilize before the first conversion. If stop mode
is exited with no delay (DLY bit in OPTION register = 0), allow 10 ms for
the A/D circuitry to stabilize to avoid invalid results.
Technical Data
230
Analog-to-Digital (A/D) Converter
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M68HC11K Family
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