K11P80M50SF4 Datasheet, PDF (51/54 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet

80
Default
LQFP
56 ADC0_SE15
57 ADC0_SE4b/
CMP1_IN0
58 CMP1_IN1
59 VSS
60 VDD
61 DISABLED
62 DISABLED
63 CMP0_IN0
64 CMP0_IN1
65 CMP0_IN2
66 CMP0_IN3
67 DISABLED
68 DISABLED
69 DISABLED
70 DISABLED
71 DISABLED
72 DISABLED
73 DISABLED
74 ADC0_SE5b
75 DISABLED
76 DISABLED
77 ADC0_SE21
78 ADC0_SE6b
ALT0
ADC0_SE15
ADC0_SE4b/
CMP1_IN0
CMP1_IN1
VSS
VDD
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
ADC0_SE5b
ADC0_SE21
ADC0_SE6b
ALT1
PTC1/
LLWU_P6
PTC2
PTC3/
LLWU_P7
PTC4/
LLWU_P8
PTC5/
LLWU_P9
PTC6/
LLWU_P10
PTC7
PTC8
PTC9
PTC10
PTC11/
LLWU_P11
PTC12
PTC13
PTC16
PTC17
PTD0/
LLWU_P12
PTD1
PTD2/
LLWU_P13
PTD3
PTD4/
LLWU_P14
PTD5
79 ADC0_SE7b
80 ADC0_SE22
ADC0_SE7b
ADC0_SE22
PTD6/
LLWU_P15
PTD7
ALT2
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
I2C1_SCL
I2C1_SDA
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
SPI0_PCS1
SPI0_PCS2
SPI0_PCS3
CMT_IRO
ALT3
ALT4
UART1_RTS_b FTM0_CH0
UART1_CTS_b FTM0_CH1
UART1_RX FTM0_CH2
UART1_TX FTM0_CH3
LPTMR0_ALT2 I2S0_RXD0
PDB0_EXTRG I2S0_RX_BCLK
I2S0_RX_FS
I2S0_MCLK
I2S0_RX_BCLK
I2S0_RX_FS
I2S0_RXD1
UART3_RX
UART3_TX
UART2_RTS_b
UART2_CTS_b
UART2_RX I2C0_SCL
UART2_TX I2C0_SDA
UART0_RTS_b FTM0_CH4
UART0_CTS_b/
UART0_COL_b
UART0_RX
FTM0_CH5
FTM0_CH6
UART0_TX FTM0_CH7
ALT5
ALT6
ALT7
I2S0_TXD0
I2S0_TX_FS
I2S0_TX_BCLK
CMP1_OUT
CMP0_OUT
I2S0_MCLK
FTM0_CH2
FTM2_FLT0
EWM_IN
EWM_OUT_b
FTM0_FLT0
FTM0_FLT1
Pinout
EzPort
8.2 K11 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Freescale Semiconductor, Inc.
51