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K11P80M50SF4 Datasheet, PDF (25/54 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet | |||
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Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol Description
Min.
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
640 Ã ffll_ref
Mid range (DRS=01)
31.25
20
40
1280 Ã ffll_ref
Mid-high range (DRS=10)
60
1920 Ã ffll_ref
High range (DRS=11)
80
fdco_t_DMX32 DCO output
frequency
2560 Ã ffll_ref
Low range (DRS=00)
â
732 Ã ffll_ref
Mid range (DRS=01)
â
1464 Ã ffll_ref
Mid-high range (DRS=10)
â
2197 Ã ffll_ref
High range (DRS=11)
â
Jcyc_fll
tfll_acquire
FLL period jitter
2929 Ã ffll_ref
⢠fVCO = 48 MHz
⢠fVCO = 98 MHz
FLL target frequency acquisition time
â
â
â
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
⢠PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
48.0
â
Ipll
PLL operating current
⢠PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
â
2 MHz, VDIV multiplier = 24)
fpll_ref PLL reference frequency range
2.0
Jcyc_pll PLL period jitter (RMS)
⢠fvco = 48 MHz
â
⢠fvco = 100 MHz
â
Typ.
Max.
Unit
â
20.97
39.0625
25
kHz
MHz
41.94
50
MHz
62.91
75
MHz
83.89
100
MHz
23.99
â
MHz
47.97
â
MHz
71.99
â
MHz
95.98
â
MHz
180
â
ps
150
â
â
1
ms
â
100
MHz
1060
â
µA
600
â
µA
â
4.0
MHz
120
â
ps
50
â
ps
Notes
2, 3
4, 5
6
7
7
8
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
⢠fvco = 48 MHz
⢠fvco = 100 MHz
8
â
1350
â
ps
â
600
â
ps
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
± 1.49
â
± 2.98
%
± 4.47
â
± 5.97
%
Table continues on the next page...
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Freescale Semiconductor, Inc.
25
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