K11P80M50SF4 Datasheet, PDF (21/54 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
2.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
3.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
5.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
6.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 JTAG electricals
Table 12. JTAG limited voltage range electricals
Symbol
J1
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
2.7
0
0
0
Max.
3.6
10
25
50
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
1/J1
—
50
—
20
—
10
—
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
J6
Boundary scan input data hold time after TCLK rise
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
J11
TCLK low to TDO data valid
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
3
20
—
0
—
—
25
—
25
8
—
1
—
—
17
—
17
100
—
8
—
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Freescale Semiconductor, Inc.
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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