K11P80M50SF4 Datasheet, PDF (34/54 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 24. 16-bit ADC operating conditions (continued)
Symbol
V_REFL
V_ADIN
C_ADIN
Description
Conditions
ADC reference
voltage low
Input voltage
Input capacitance • 16-bit mode
• 8-/10-/12-bit modes
Min.
V_SSA
V_REFL
—
—
Typ.¹
V_SSA
—
8
4
Max.
V_SSA
V_REFH
10
5
Unit
V
V
pF
R_ADIN
R_AS
Input resistance
Analog source
resistance
13-/12-bit modes
f_ADCK < 4 MHz
—
2
5
kΩ
—
—
5
kΩ
Notes
3
f_ADCK
ADC conversion ≤ 13-bit mode
clock frequency
1.0
—
18.0
MHz
4
f_ADCK
ADC conversion 16-bit mode
clock frequency
2.0
—
12.0
MHz
4
C_rate ADC conversion ≤ 13 bit modes
5
rate
No ADC hardware averaging 20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
C_rate ADC conversion 16-bit mode
5
rate
No ADC hardware averaging 37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume V_DDA = 3.0 V, Temp = 25 °C, f_ADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best
results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The R_AS/C_AS
time constant should be kept to < 1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
34
Freescale Semiconductor, Inc.