MC68HC908QY4CDW Datasheet, PDF (5/184 Pages) Freescale Semiconductor, Inc – Microcontrollers

Revision History (Sheet 2 of 3)
Date
August,
2003
October,
2003
January,
2004
Revision
Level
1.0
2.0
3.0
Description
Reformatted to meet latest M68HC08 documentation standards
Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt
module and TCLK pin designator.
Figure 1-2. MCU Pin Assignments — Added TCLK pin designator.
Table 1-2. Pin Functions — Added TCLK pin description.
Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to
add TCLK.
Figure 2-1. Memory Map — Corrected names for the IRQ status and control
register (INTSCR) bits 3–0.
3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock
prescaler bits.
4.3 Functional Description — Updated periodic wakeup request values.
Figure 6-1. COP Block Diagram — Reworked for clarity
Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF,
ACK, and IMASK
Chapter 14 Timer Interface Module (TIM) — Added TCLK function.
15.3 Monitor Module (MON) — Updated with additional data.
Chapter 16 Electrical Specifications — Updated with additional data.
Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented
areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available.
Also corrected $FFBF designation from unimplemented to reserved.
Figure 6-1. COP Block Diagram — Reworked for clarity
6.3.2 STOP Instruction — Added subsection
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity.
Table 13-2. Reset Recovery Timing — Replaced previous table with new
information.
Chapter 14 Timer Interface Module (TIM) — Updated with additional data.
Figure 15-3. Break I/O Register Summary — Corrected bit designators for the
BRKAR register
15.3 Monitor Module (MON) — Clarified seventh bullet.
Table 17-1. MC Order Numbers — Corrected temperature and package
designators.
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal
Oscillator Trim Value at $FFC0.
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for
clarity.
Page
Number(s)
N/A
20
21
22
23
26
47
51
59
77–79
131–139
147
169–173
27
59
60
111
112
131
143
147
175
32
38
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
5