|
MC68HC908QY4CDW Datasheet, PDF (27/184 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
|
◁ |
Input/Output (I/O) Section
2.4 Input/Output (I/O) Section
Addresses $0000â$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have these addresses:
⢠$FE00 â Break status register, BSR
⢠$FE01 â Reset status register, SRSR
⢠$FE02 â Break auxiliary register, BRKAR
⢠$FE03 â Break flag control register, BFCR
⢠$FE04 â Interrupt status register 1, INT1
⢠$FE05 â Interrupt status register 2, INT2
⢠$FE06 â Interrupt status register 3, INT3
⢠$FE07 â Reserved
⢠$FE08 â FLASH control register, FLCR
⢠$FE09 â Break address register high, BRKH
⢠$FE0A â Break address register low, BRKL
⢠$FE0B â Break status and control register, BRKSCR
⢠$FE0C â LVI status register, LVISR
⢠$FE0D â Reserved
⢠$FFBE â FLASH block protect register, FLBPR
⢠$FFC0 â Internal OSC trim value (factory programmed, VDD = 5.0 V)
⢠$FFC1 â Internal OSC trim value (factory programmed, VDD = 3.0 V)
⢠$FFFF â COP control register, COPCTL
Addr.
$0000
$0001
$0002
Register Name
Port A Data Register
(PTA)
See page 98.
Port B Data Register
(PTB)
See page 100.
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
R
PTB7
6
AWUL
5
PTA5
PTB6
PTB5
4
3
PTA4
PTA3
Unaffected by reset
PTB4
PTB3
Unaffected by reset
2
PTA2
PTB2
1
PTA1
PTB1
Bit 0
PTA0
PTB0
$0003
Unimplemented
$0004
$0005
Data Direction Register A
(DDRA)
See page 98.
Data Direction Register B
(DDRB)
See page 101.
Read:
Write:
Reset:
Read:
Write:
Reset:
R
0
DDRB7
0
R
DDRA5
0
0
DDRB6 DDRB5
0
0
= Unimplemented
0
DDRA4 DDRA3
DDRA1
0
0
0
0
DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
DDRA0
0
DDRB0
0
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
27
|
▷ |