MC68HC908QY4CDW Datasheet, PDF (104/184 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
V_DD
INTERNAL
PULL-UP
÷2
CLOCK
CONTROL
CLOCK GENERATORS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
FORCED MON MODE ENTRY (FROM MENRST MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 13-1. SIM Block Diagram
13.2 RST and IRQ Pins Initialization
RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be
activated by programing CONFIG2 accordingly. Refer to Chapter 5 Configuration Register (CONFIG).
13.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-2.
MC68HC908QY/QT Family Data Sheet, Rev. 6
104
Freescale Semiconductor