MC68HC908QY4CDW Datasheet, PDF (145/184 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor Module (MON)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
FROM
HOST
READ
READ
ADDRESS ADDRESS ADDRESS ADDRESS
HIGH
HIGH
LOW
LOW
4
1
4
1
4
1
3, 2
DATA
4
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
RETURN
Figure 15-15. Read Transaction
FROM
HOST
WRITE
WRITE
ADDRESS ADDRESS ADDRESS ADDRESS
HIGH
HIGH
LOW
LOW
DATA
DATA
3
1
3
1
3
1
3
1
2, 3
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-16. Write Transaction
A brief description of each monitor mode command is given in Table 15-3 through Table 15-8.
Table 15-3. READ (Read Memory) Command
Description
Operand
Data Returned
Opcode
Read byte from memory
2-byte address in high-byte:low-byte order
Returns contents of specified address
$4A
Command Sequence
SENT TO MONITOR
READ
READ
ADDRESS ADDRESS ADDRESS ADDRESS
HIGH
HIGH
LOW
LOW
ECHO
DATA
RETURN
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
145