MC68HC908QY4CDW Datasheet, PDF (144/184 Pages) Freescale Semiconductor, Inc – Microcontrollers

Development Support
Table 15-2. Mode Difference
Modes
User
Monitor
Reset
Vector High
$FFFE
$FEFE
Reset
Vector Low
$FFFF
$FEFF
Functions
Break
Break
Vector High Vector Low
$FFFC
$FFFD
$FEFC
$FEFD
SWI
Vector High
$FFFC
$FEFC
SWI
Vector Low
$FFFD
$FEFD
15.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT BIT 0
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT
START
BIT 6 BIT 7 STOP BIT
BIT
Figure 15-13. Monitor Data Format
15.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
01234567
01234567
Figure 15-14. Break Transaction
15.3.1.6 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external or internal oscillator
and the state of the appropriate pins as shown in Table 15-1.
Table 15-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the
bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in
forced monitor mode, the effective baud rate is the bus frequency divided by 335.
15.3.1.7 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
MC68HC908QY/QT Family Data Sheet, Rev. 6
144
Freescale Semiconductor