MSC7118 Datasheet, PDF (47/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller

Hardware Design Considerations
3.2.7 Power Supply Design
One of the most common ways to derive power is to use either a simple fixed or adjustable linear regulator. For the system I/O
voltage supply, a simple fixed 3.3 V supply can be used. However, a separate adjustable linear regulator supply for the core
voltage V_DDC should be implemented. For the memory power supply, regulators are available that take care of all DDR power
requirements.
Table 29. Recommended Power Supply Ratings
Supply
Core
Memory
Reference
I/O
Symbol
V_DDC
V_DDM
V_REF
V_DDIO
Nominal Voltage
1.2 V
2.5 V
1.25 V
3.3 V
Current Rating
1.5 A per device
0.5 A per device
10 µA per device
1.0 A per device
3.3 Estimated Power Usage Calculations
The following equations permit estimated power usage to be calculated for individual design conditions. Overall power is
derived by totaling the power used by each of the major subsystems:
P_TOTAL = P_CORE + P_PERIPHERALS + P_DDRIO + P_IO + P_LEAKAGE
Eqn. 3
This equation combines dynamic and static power. Dynamic power is determined using the generic equation:
C × V² × F × 10^–3 mW
Eqn. 4
where,
C = load capacitance in pF
V = peak-to-peak voltage swing in V
F = frequency in MHz
3.3.1 Core Power
Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core load
capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 300 MHz. This yields:
P_CORE = 750 pF × (1.2 V)² × 300 MHz × 10^–3 = 324.0 mW
Eqn. 5
This equation allows for adjustments to voltage and frequency if necessary.
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Freescale Semiconductor
47