MSC7118 Datasheet, PDF (30/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller

Electrical Characteristics
2.5.6 HDI16 Signals
Table 21. Host Interface (HDI16) Timing^{1, 2}
No.
40
44a
44b
44c
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
62
63
64
Notes:
Characteristics³
Expression
Value
Unit
Host Interface Clock period
Read data strobe minimum assertion width⁴
HACK read minimum assertion width
T_CORE
Note 1
ns
2.0 × T_CORE + 9.0
Note 11
ns
Read data strobe minimum deassertion width⁴
HACK read minimum deassertion width
1.5 × T_CORE
Note 11
ns
Read data strobe minimum deassertion width⁴ after “Last Data Register”
reads^5,6, or between two consecutive CVR, ICR, or ISR reads⁷
HACK minimum deassertion width after “Last Data Register” reads^5,6
2.5 × T_CORE
Note 11
ns
Write data strobe minimum assertion width⁸
HACK write minimum assertion width
1.5 × T_CORE
Note 11
ns
Write data strobe minimum deassertion width⁸
HACK write minimum deassertion width after ICR, CVR and Data Register
writes⁵
Host data input minimum setup time before write data strobe deassertion⁸
Host data input minimum setup time before HACK write deassertion
Host data input minimum hold time after write data strobe deassertion⁸
2.5 × T_CORE
—
Note 11
ns
2.5
ns
Host data input minimum hold time after HACK write deassertion
—
2.5
ns
Read data strobe minimum assertion to output data active from high
impedance⁴
HACK read minimum assertion to output data active from high impedance
—
1.0
ns
Read data strobe maximum assertion to output data valid⁴
HACK read maximum assertion to output data valid
(2.0 × T_CORE) + 8.0
Note 11
ns
Read data strobe maximum deassertion to output data high impedance⁴
HACK read maximum deassertion to output data high impedance
—
9.0
ns
Output data minimum hold time after read data strobe deassertion⁴
Output data minimum hold time after HACK read deassertion
HCS[1–2] minimum assertion to read data strobe assertion⁴
HCS[1–2] minimum assertion to write data strobe assertion⁸
—
1.0
ns
—
0.5
ns
—
0.0
ns
HCS[1–2] maximum assertion to output data valid
HCS[1–2] minimum hold time after data strobe deassertion⁹
HA[0–2], HRW minimum setup time before data strobe assertion⁹
HA[0–2], HRW minimum hold time after data strobe deassertion⁹
(2.0 × T_CORE) + 6.0
Note 11
ns
—
0.5
ns
—
5.0
ns
—
5.0
ns
Maximum delay from read data strobe deassertion to host request
deassertion for “Last Data Register” read^{4, 5, 10}
(3.0 × T_CORE) + 6.0
Note 11
ns
Maximum delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write^5,8,10
(3.0 × T_CORE) + 6.0
Note 11
ns
Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
(2.0 × T_CORE) + 1.0
Note 11
ns
Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
(5.0 × T_CORE) + 6.0
Note 11
ns
1. T_CORE = core clock period. At 300 MHz, T_CORE = 3.333 ns.
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. V_DD = 3.3 V ± 0.15 V; T_J = –40°C to +105 °C, C_L = 30 pF for maximum delay timings and C_L = 0 pF for minimum delay timings.
4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5. For 64-bit transfers, the “last data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6. This timing is applicable only if a read from the “last data register” is followed by a read from the RX[0–3] registers without first
polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7. This timing is applicable only if two consecutive reads from one of these registers are executed.
8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
11. Compute the value using the expression.
12. The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe
modes is based on timings 57 and 58.
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
30
Freescale Semiconductor