MSC7118 Datasheet, PDF (45/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller

Hardware Design Considerations
3.2.2.5 Case 5 (not recommended for new designs)
The power-up sequence is as follows:
1. Turn on the V_DDIO (3.3 V) supply first.
2. Turn on the V_DDM (2.5 V) supply second.
3. Turn on the V_DDC (1.2 V) supply third.
4. Turn on the V_REF (1.25 V) supply fourth (last).
Note: Make sure that the time interval between the ramp-up of V_DDIO and V_DDM is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the V_REF (1.25 V) supply first.
2. Turn off the V_DDC (1.2 V) supply second.
3. Turn off the V_DDM (2.5 V) supply third.
4. Turn of the V_DDIO (3.3 V) supply fourth (last).
Use the following guidelines:
• Make sure that the time interval between the ramp-down of V_DDIO and V_DDM is less than 10 ms.
• Make sure that the time interval between the ramp-up or ramp-down for V_DDC and V_DDM is less than 2 ms for
power-up and power-down.
• Refer to Figure 30 for relative timing for power sequencing case 5.
Ramp-up
Ramp-down
V_DDIO = 3.3 V
V_DDM = 2.5 V
<2 ms
<10 ms
<2 ms
<10 ms
V_REF = 1.25 V
V_DDC = 1.2 V
Time
Figure 30. Voltage Sequencing Case 5
Note: Cases 1, 2, 3, and 4 are recommended for system design. Designs that use Case 5 may have large current spikes on
the V_DDM supply at startup and is not recommended for most designs. If a design uses case 5, it must accommodate
the potential current spikes. Verify risks related to current spikes using actual information for the specific application.
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Freescale Semiconductor
45