MSC7118 Datasheet, PDF (23/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller

Electrical Characteristics
2.5.2.3 Multiplication Factor Range
The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10.
Table 10. PLLMLTF Ranges
Multiplier Block (Loop) Output Range
Minimum PLLMLTF Value Maximum PLLMLTF Value
266 ≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz
266/Divided Input Clock
532/Divided Input Clock
Note:
This table results from the allowed range for F_Loop. The minimum and maximum multiplication factors are dependent on the
frequency of the Divided Input Clock.
2.5.2.4 Allowed Core Clock Frequency Range
The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown
in Table 11.
Table 11. F_vco Frequency Ranges
CLKCTRL[RNG] Value
Allowed Range of F_vco
Note:
1
266 ≤ F_vco ≤ 532 MHz
0
133 ≤ F_vco ≤ 266 MHz
This table results from the allowed range for F_vco, which is F_Loop modified by CLKCTRL[RNG].
This bit along with the CKSEL determines the frequency range of the core clock.
Table 12. Resulting Ranges Permitted for the Core Clock
CLKCTRL[CKSEL]
CLKCTRL[RNG]
Resulting
Division
Factor
Allowed Range
of Core Clock
Comments
Note:
11
1
1
266 ≤ core clock ≤ 300 MHz
Limited by maximum core
frequency
11
0
2
133 ≤ core clock ≤ 266 MHz
Limited by range of PLL
01
1
2
133 ≤ core clock ≤ 266 MHz
Limited by range of PLL
01
0
4
66.5 ≤ core clock ≤ 133 MHz
Limited by range of PLL
This table results from the allowed range for F_OUT, which depends on clock selected via CLKCTRL[CKSEL].
2.5.2.5 Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this
restriction.
DDR Type
DDR 200 (PC-1600)
DDR 266 (PC-2100)
DDR 333 (PC-2600)
Table 13. Core Clock Ranges When Using DDR
Allowed Frequency
Range for DDR CK
83–100 MHz
83–133 MHz
83–150 MHz
Corresponding Range
for the Core Clock
166 ≤ core clock ≤ 200 MHz
166 ≤ core clock ≤ 266 MHz
166 ≤ core clock ≤ 300 MHz
Comments
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Freescale Semiconductor
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