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K50P100M100SF2 Datasheet, PDF (47/73 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz | |||
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Peripheral operating requirements and behaviors
Table 28. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
VH
Description
Analog comparator hysteresis1
⢠CR0[HYSTCTR] = 00
⢠CR0[HYSTCTR] = 01
⢠CR0[HYSTCTR] = 10
⢠CR0[HYSTCTR] = 11
Min.
Typ.
Max.
Unit
â
5
â
mV
â
10
â
mV
â
20
â
mV
â
30
â
mV
VCMPOh
VCMPOl
tDHS
tDLS
IDAC6b
INL
DNL
Output high
Output low
Propagation delay, high-speed mode (EN=1,
PMODE=1)
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
VDD â 0.5
â
â
â
20
50
120
250
â
â
â
7
â0.5
â
â0.3
â
â
0.5
200
600
TBD
â
0.5
0.3
V
V
ns
ns
ns
μA
LSB3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
47
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