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K50P100M100SF2 Datasheet, PDF (14/73 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz | |||
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General
5.1.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSxâRUN recovery times in the following table
assume this clock configuration:
⢠CPU and system clocks = 100 MHz
⢠Bus and FlexBus clocks = 50 MHz
⢠Flash clock = 25 MHz
Symbol
tPOR
Table 5. Power mode transition operating behaviors
Description
Min.
Max.
Unit
After a POR event, amount of time from the point VDD
â
300
μs
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
RUN â VLLS1 â RUN
⢠RUN â VLLS1
â
4.1
μs
⢠VLLS1 â RUN
â
123.8
μs
Notes
1
RUN â VLLS2 â RUN
⢠RUN â VLLS2
⢠VLLS2 â RUN
â
4.1
μs
â
49.3
μs
RUN â VLLS3 â RUN
⢠RUN â VLLS3
⢠VLLS3 â RUN
â
4.1
μs
â
49.2
μs
RUN â LLS â RUN
⢠RUN â LLS
⢠LLS â RUN
â
4.1
μs
â
5.9
μs
RUN â STOP â RUN
⢠RUN â STOP
⢠STOP â RUN
â
4.1
μs
â
4.2
μs
RUN â VLPS â RUN
⢠RUN â VLPS
⢠VLPS â RUN
â
4.1
μs
â
5.8
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
14
Preliminary
Freescale Semiconductor, Inc.
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