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K50P100M100SF2 Datasheet, PDF (45/73 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz | |||
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Peripheral operating requirements and behaviors
Table 27. 16-bit ADC with PGA characteristics (continued)
Symbol
CMRR
Description
Common mode
rejection ratio
Conditions
⢠Gain=1
⢠Gain=64
VOFS
TGSW
dG/dT
Input offset
voltage
Gain switching
settling time
Gain drift over
temperature
dVOFS/dT Offset drift over
temperature
dG/dVDDA Gain drift over
supply voltage
EIL
Input leakage
error
⢠Gain=1
⢠Gain=64
Gain=1
⢠Gain=1
⢠Gain=64
All modes
VPP,DIFF
Maximum
differential input
signal swing
SNR
Signal-to-noise
ratio
⢠Gain=1
⢠Gain=64
THD
Total harmonic
distortion
⢠Gain=1
⢠Gain=64
SFDR
Spurious free
dynamic range
⢠Gain=1
⢠Gain=64
Min.
TBD
TBD
â
â
Typ.1
TBD
TBD
Max.
â
â
0.2
TBD
â
10
Unit
Notes
dB
VCM=
dB
500mVpp,
fVCM= 50Hz,
100Hz
mV
Gain=1, ADC
Averaging=32
µs
5
â
TBD
TBD ppm/°C 0 to 50°C
â
TBD
TBD ppm/°C
â
TBD
TBD ppm/°C 0 to 50°C, ADC
Averaging=32
â
TBD
TBD
%/V VDDA from 1.71
â
TBD
TBD
%/V
to 3.6V
IIn à RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
V
6
where VX = VREFPGA Ã 0.583
TBD
83.0
â
dB
TBD
57.5
â
dB
TBD
89.4
â
dB
TBD
90.0
â
dB
TBD
90.9
â
dB
TBD
77.0
â
dB
16-bit
differential
mode,
Average=32
16-bit
differential
mode,
Average=32,
fin=500Hz
16-bit
differential
mode,
Average=32,
fin=500Hz
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
45
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