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K50P100M100SF2 Datasheet, PDF (26/73 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz | |||
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Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
Iintf
Internal reference (fast clock) current
â
tirefstf Internal reference startup time (fast clock)
â
floc_low
Loss of external clock minimum frequency â
RANGE = 00
(3/5) x
fints_t
floc_high Loss of external clock minimum frequency â
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref FLL reference frequency range
31.25
fdco
DCO output
Low range (DRS=00)
20
frequency range
640 Ã ffll_ref
Mid range (DRS=01)
40
1280 Ã ffll_ref
Mid-high range (DRS=10)
60
1920 Ã ffll_ref
High range (DRS=11)
80
2560 Ã ffll_ref
fdco_t_DMX3 DCO output
2
frequency
Low range (DRS=00)
â
732 Ã ffll_ref
Mid range (DRS=01)
â
1464 Ã ffll_ref
Mid-high range (DRS=10)
â
2197 Ã ffll_ref
High range (DRS=11)
â
2929 Ã ffll_ref
Jcyc_fll FLL period jitter
â
Jacc_fll FLL accumulated jitter of DCO output over a 1µs
â
time window
tfll_acquire FLL target frequency acquisition time
â
PLL
fvco
VCO operating frequency
48.0
Ipll
PLL operating current
⢠PLL @ 96 MHz (fosc_hi_1=8MHz,
â
fpll_ref=2MHz, VDIV multiplier=48)
fpll_ref PLL reference frequency range
2.0
Jcyc_pll PLL period jitter
â
Jacc_pll PLL accumulated jitter over 1µs window
â
Typ.
TBD
TBD
â
â
â
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
TBD
TBD
â
â
950
â
400
TBD
Max.
â
TBD
â
â
39.0625
25
50
75
100
â
â
â
â
TBD
TBD
1
100
â
4.0
â
â
Table continues on the next page...
Unit
µA
µs
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ms
MHz
µA
MHz
ps
ps
Notes
2, 3
4, 5
6
6
7
8
9, 10
9, 10
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
26
Preliminary
Freescale Semiconductor, Inc.
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