K20P120M100SF2 Datasheet, PDF (45/66 Pages) Freescale Semiconductor, Inc – K20 Data Sheet

Peripheral operating requirements and behaviors
Table 31. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
t_DLS
I_DAC6b
INL
DNL
Description
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay²
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
Min.
80
—
—
–0.5
–0.3
Typ.
250
—
7
—
—
Max.
600
40
—
0.5
0.3
Unit
ns
μs
μA
LSB³
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = V_reference/64
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vin level (V)
Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K20 Data Sheet Data Sheet, Rev. 6.1, 08/2012.
Freescale Semiconductor, Inc.
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