MC912D60ACFUE8 Datasheet, PDF (420/460 Pages) Freescale Semiconductor, Inc – MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data

Electrical Specifications
Num
Table 20-14. Multiplexed Expansion Bus Timing
V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted
Characteristic^{(1), (2), (3), (4)}
8 MHz
Delay Symbol
Unit
Min Max
Frequency of operation (ECLK frequency)
1 Cycle timet_cyc = 1/f_o
2 Pulse width, E lowPW_EL = t_cyc/2 + delay
3 Pulse width, E high⁽⁵⁾PW_EH = t_cyc/2 + delay
5 Address delay timet_AD = t_cyc/4 + delay
7 Address valid time to ECLK riset_AV = PW_EL − t_AD
8 Multiplexed address hold timet_MAH = t_cyc/4 + delay
9 Address Hold to Data Valid
10 Data Hold to High Zt_DHZ = t_AD − 20
11 Read data setup time
12 Read data hold time
13 Write data delay time
14 Write data hold time
15 Write data setup time⁽⁵⁾t_DSW = PW_EH − t_DDW
16 Read/write delay timet_RWD = t_cyc/4 + delay
17 Read/write valid time to E riset_RWV = PW_EL − t_RWD
18 Read/write hold time
19 Low strobe⁽⁶⁾ delay timet_LSD = t_cyc/4 + delay
20 Low strobe⁽⁶⁾ valid time to E riset_LSV = PW_EL − t_LSD
21 _{Low strobe}⁽⁶⁾ _{hold time}
f_o 0.004 8.0 MHz
—
t_cyc 0.125 250 µs
−4 PW_EL 58
ns
−2 PW_EH 60
ns
27
t_AD
50 ns
—
t_AV
8
ns
−18 t_MAH 13
ns
—
t_AHDS 20
ns
—
t_DHZ
30 ns
—
t_DSR 25
ns
—
t_DHR
0
ns
—
t_DDW
47 ns
—
t_DHW 20
ns
—
t_DSW 13
ns
18
t_RWD
49 ns
—
t_RWV
9
ns
—
t_RWH 20
ns
18
t_LSD
49 ns
—
t_LSV
9
ns
—
t_LSH
20
ns
22 Address access time⁽⁵⁾t_ACCA = t_cyc − t_AD − t_DSR
23 Access time from E rise⁽⁵⁾t_ACCE = PW_EH − t_DSR
24 DBE delay from ECLK rise⁽⁵⁾t_DBED = t_cyc/4 + delay
25 DBE valid timet_DBE = PW_EH − t_DBED
26 DBE hold time from ECLK fall
—
t_ACCA
50 ns
—
t_ACCE
35 ns
8
t_DBED
39 ns
—
t_DBE
21
ns
t_DBEH 0 10 ns
1. All timings are calculated for normal port drives.
2. Crystal input is required to be within 45% to 55% duty.
3. Reduced drive must be off to meet these timings.
4. Unequalled loading of pins will affect relative timing numbers.
5. This characteristic is affected by clock stretch.
Add N × t_cyc where N = 0, 1, 2, or 3, depending on the number of clock stretches.
6. Without TAG enabled.
Technical Data
420
Electrical Specifications
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor