MC912D60ACFUE8 Datasheet, PDF (221/460 Pages) Freescale Semiconductor, Inc – MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pulse Width Modulator
PWM Register Description
Bit 7
6
5
PP7
PP6
PP5
PWM
–
–
–
RESET:
–
–
–
PORTP — Port P Data Register
4
3
2
1
Bit 0
PP4
PP3
PP2
PP1
PP0
–
PWM3
PWM2
PWM1
PWM0
–
–
–
–
–
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PORTP can be read anytime.
PWM functions share port P pins 3 to 0 and take precedence over the
general-purpose port when enabled.
When configured as input, a read will return the pin level.
When configured as output, a read will return the latched output data.
A write will drive associated pins only if configured for output and the
corresponding PWM channel is not enabled.
After reset, all pins are general-purpose, high-impedance inputs.
Bit 7
6
5
DDP7
DDP6
DDP5
RESET:
0
0
0
DDRP — Port P Data Direction Register
4
DDP4
0
3
DDP3
0
2
DDP2
0
1
DDP1
0
Bit 0
DDP0
0
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DDRP determines pin direction of port P when used for general-purpose
I/O.
Read and write anytime.
DDRP[7:0] — Data Direction Port P pin 7-0
0 = I/O pin configured as high impedance input
1 = I/O pin configured for output.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Pulse Width Modulator
Technical Data
221