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MC912D60ACFUE8 Datasheet, PDF (209/460 Pages) Freescale Semiconductor, Inc – MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data | |||
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Pulse Width Modulator
Introduction
CLOCK SOURCE
(ECLK or Scaled ECLK)
GATE
(CLOCK EDGE SYNC)
PWENx
SYNC
PPOL = 1
PPOL = 0
PWDTY
PWCNTx
CENTR = 1
RESET
(DUTY CYCLE)
8-BIT COMPARE =
PWDTYx
(PERIOD)
8-BIT COMPARE =
PWPERx
FROM PORT P
DATA REGISTER
T
Q MUX
Q
PPOLx
MUX
TO PIN
DRIVER
(PWPER â PWDTY) Ã 2
PWPER Ã 2
PWDTY
Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel
MC68HC912D60A â Rev. 3.1
Freescale Semiconductor
Pulse Width Modulator
Technical Data
209
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