MC912D60ACFUE8 Datasheet, PDF (100/460 Pages) Freescale Semiconductor, Inc – MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data

Flash Memory
FEESWAI — Flash EEPROM Stop in Wait Control
0 = Do not halt Flash EEPROM clock when the part is in wait mode.
0 = Halt Flash EEPROM clock when the part is in wait mode.
HVEN — High-Voltage Enable
This bit enables the charge pump to supply high voltages for program
and erase operations in the array. HVEN can only be set if either PGM
or ERAS are set and the proper sequence for program or erase is
followed.
0 = Disables high voltage to array and charge pump off
1 = Enables high voltage to array and charge pump on
ERAS — Erase Control
This bit configures the memory for erase operation. ERAS is
interlocked with the PGM bit such that both bits cannot be equal to 1
or set to1 at the same time.
0 = Erase operation is not selected.
1 = Erase operation selected.
PGM — Program Control
This bit configures the memory for program operation. PGM is
interlocked with the ERAS bit such that both bits cannot be equal to 1
or set to1 at the same time.
0 = Program operation is not selected.
1 = Program operation selected.
7.7 Operation
The Flash EEPROM can contain program and data. On reset, it can
operate as a bootstrap memory to provide the CPU with internal
initialization information during the reset sequence.
7.7.1 Bootstrap Operation Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by
fetching the first program address from address $FFFE.
Technical Data
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Flash Memory
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor