MC912D60ACFUE8 Datasheet, PDF (220/460 Pages) Freescale Semiconductor, Inc – MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pulse Width Modulator
RDPP — Reduced Drive of Port P
0 = All port P output pins have normal drive capability.
1 = All port P output pins have reduced drive capability.
PUPP — Pull-Up Port P Enable
0 = All port P pins have an active pull-up device disabled.
1 = All port P pins have an active pull-up device enabled.
PSBCK — PWM Stops while in Background Mode
0 = Allows PWM to continue while in background mode.
1 = Disable PWM input clock when the part is in background mode.
Bit 7
6
5
4
3
2
1
Bit 0
DISCR DISCP DISCAL
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
PWTST — PWM Special Mode Register (“Test”)
$0055
Read anytime but write only in special mode (SMODN = 0). These bits
are available only in special mode and are reset in normal mode.
DISCR — Disable Reset of Channel Counter on Write to Channel
Counter
0 = Normal operation. Write to PWM channel counter will reset
channel counter.
1 = Write to PWM channel counter does not reset channel counter.
DISCP — Disable Compare Count Period
0 = Normal operation
1 = In left-aligned output mode, match of period does not reset the
associated PWM counter register.
DISCAL — Disable Load of Scale-Counters on Write to the Associated
Scale-Registers
0 = Normal operation
1 = Write to PWSCAL0 and PWSCAL1 does not load scale
counters
Technical Data
220
Pulse Width Modulator
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor