MC912D60ACFUE8 Datasheet, PDF (286/460 Pages) Freescale Semiconductor, Inc – MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
DDS2, DDS0 — Data Direction for Port S Bit 2 and Bit 0
If the SCI receiver is configured for two-wire SCI operation,
corresponding port S pins will be input regardless of the state of these
bits.
DDS3, DDS1 — Data Direction for Port S Bit 3 and Bit 1
If the SCI transmitter is configured for two-wire SCI operation,
corresponding port S pins will be output regardless of the state of
these bits.
DDS[6:4] — Data Direction for Port S Bits 6 through 4
If the SPI is enabled and expects the corresponding port S pin to be
an input, it will be an input regardless of the state of the DDRS bit. If
the SPI is enabled and expects the bit to be an output, it will be an
output ONLY if the DDRS bit is set.
DDS7 — Data Direction for Port S Bit 7
In SPI slave mode, DDRS7 has no meaning or effect; the PS7 pin is
dedicated as the SS input. In SPI master mode, DDRS7 determines
whether PS7 is an error detect input to the SPI or a general-purpose
or slave select output line.
NOTE: If mode fault error occurs, bits 5, 6 and 7 are forced to zero.
Technical Data
286
Multiple Serial Interface
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor