MC912D60ACFUE8 Datasheet, PDF (413/460 Pages) Freescale Semiconductor, Inc – MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data

Electrical Specifications
Tables of Data
Table 20-12. Control Timing
Characteristic
Frequency of operation
ECLK period
External oscillator frequency
Processor control setup time
t_PCSU = t_cyc/2 + 20
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be preempted by internal reset)
Mode programming setup time
Mode programming hold time
Interrupt pulse width, IRQ edge-sensitive mode
PW_IRQ = 2t_cyc + 20
Wait recovery startup time
Timer input capture pulse width
PW_TIM = 2t_cyc + 20
1. When using a quartz crystal, see Table 20-17 for allowable values.
Symbol
f_o
t_cyc
f_eo
t_PCSU
PW_RSTL
t_MPS
t_MPH
PW_IRQ
t_WRS
PW_TIM
8.0 MHz
Min Max
0.004 8.0
0.125 250
0.5 _16.0⁽¹⁾
Unit
MHz
µs
MHz
82.5 —
ns
32
—
t_cyc
2
—
t_cyc
4
—
t_cyc
10
—
ns
270 —
ns
—
4
t_cyc
270 —
ns
NOTE:
RESET is recognized during the first clock cycle it is held low. Internal
circuitry then drives the pin low for 16 clock cycles, releases the pin, and
samples the pin level 9 cycles later to determine the source of the
interrupt.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Electrical Specifications
Technical Data
413