LP1071 Datasheet, PDF (4/32 Pages) Freescale Semiconductor, Inc – 802.11a/b/g Baseband System

Functional Description
Feature
Semiconductor Technology
RF Support
Certification
Table 1. Specifications (continued)
Details
0.18 micron
Airoha, Maxim
Wi-Fi® (incl. WPA), WQHL, FCC Part 15
3 Functional Description
Figure 1 is a functional block diagram of the LP1071, which is divided into three main subsystems.
On-Chip
ARM7TDMI ^RAM/ROM
ARM
Subsystem
Bridge
Memory
Controller
AHB
UART
JTAG
EEPROM
Interface
GPIO
RMB
Registers
Watchdog
Timer
Interrupt
Controller
SDIO
Registers
Clock
Control
Clock
Gating
Shared
Memory
MAC Subsystem
Protocol
Accelerator
Subsystem
Shared
Memory
Controller
ARM
Interface
WEP
Engine
Generic
Host
Interface
AHB
AES
Engine
802.11
Protocol
Accelerator
DMA
SDIO
Interface
LP1071 Chip Boundary
PHY
Subsystem
ARM
Interface
MAC-PHY
Interface
WBSP^TM
Clock Select
Logic
PLL
AFE
AFE
Control
I/Q ADC
I/Q DAC
Aux ADC
Aux DAC
RSSI
ADC
Figure 1. Functional Block Diagram
CLKIN
(From TCXO)
3.1 Embedded Processor Subsystem
The embedded Processor Subsystem consists of the following:
• An embedded ARM7TDMI microprocessor running at 88 MHz
• An ARM® Peripheral Subsystem accessed via an extended APB (APB+) bus
3.1.1 UART
The UART is used for testing and diagnostic purposes and is capable of supporting data transfer rates of
up to 115.2 kbps.
LP1071 Advance Information, Rev. 0.5
4
Freescale Semiconductor
PRELIMINARY