LP1071 Datasheet, PDF (15/32 Pages) Freescale Semiconductor, Inc – 802.11a/b/g Baseband System

Timers/Reset
Table 8. SDIO Function 1 Registers (continued)
Bit
Name
Description
ARM
Access
8 Kbyte Internal Memory Buffer RAM (offset 0x4000 to 0x5FFF)
7:0
Imem_rdat[15:0]
This is an internal memory buffer for specific use
—
by the SDIO device. Data is read or written to this
memory via SDIO cmd 53 reads or writes. Then,
the SDIO DMA controller is used to move the data
from the internal memory buffer to/from shared
memory under device (ARM) control.
HOST
Access
RW
Reset
—
4.2 RF Interface
4.2.1 Serial Programmable Interface (SPI)
• The SPI is composed of 3 signals:
1. RF_SIF_0_SCLK (serial clock)
2. RF_SIF_1_CS_N (chip select)
3. RF_SIF_2_DIN (data input)
• The serial information is sent to the RF transceiver in 18 bit bursts framed by chip select. The 18
bits comprises of leading 14 (or less) data bits and trailing 4 address bits
• Programming clock edges are ignored until chip select goes active low.
• All bits are shifted in on the rising edge of the clock and latched in when chip select returns inactive
high. (permissible for the clock in either state)
• The interface can be programmed in any operating mode.
• Serial information is clocked in with the most significant bit (MSB) first.
• The address bits for the internal registers are decoded on the rising edge of chip select.
• The rising edge of chip select initiates an internal parallel load pulse that latches the last 18-bit
serially shifted-in data into the internal register.
5 Timers/Reset
The TCXO generates the 40 MHz RFIC 800 mV clipped sine wave reference clock.
The TCXO output is converted to a digital signal via a clock squarer input pad circuit. The 40 MHz TCXO
reference is used to generate the 40 MHz IQDAC clock and the 20 MHz IQADC clock. The PLL
synthesizes a reference from the 40 MHz reference. The reference is then used to generate the BRC, ARM,
PAS and Symbol Processor clocks, the 44 MHz IQ DAC clock and the 22 MHz IQ ADC clock. When the
TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock.
The TCXO, PLL and XTAL clock references all include bypass MUXes which allow the individual clock
reference to be driven by an external signal.
Figure 3 illustrates the high level clocking of the LP1071 with the associated pins.
LP1071 Advance Information, Rev. 0.5
Freescale Semiconductor
15
PRELIMINARY