LP1071 Datasheet, PDF (18/32 Pages) Freescale Semiconductor, Inc – 802.11a/b/g Baseband System

Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name
Pad Type Direction
Description
Pin
Clocks and Resets and Mode
EMBEDDED_RESET_N
pdisdgz
PLL_BYPASS
pdidgz
PLL_BYPASS_CLK
pdidgz
AVDD_PLL
pdiana2p
AVSS_PLL
pdiana2p
TAVDDPOWER
pvdd3p
TAVssPOWER
pvss3p
DVDD_PLL
pdiana2p
DVSS_PLL
pdiana2p
TXCO_BYPASS
pdidgz
TXCO_BYPASS_CLK
pdidgz
XTAL_BYPASS
pdidgz
XTAL_BYPASS_CLK
FAST_CLK_POWER
XTAL_32K_XIN
pdidgz
pdo02cdg
pdxoe4dg
XTAL_32K_XOUT
RESET_N
CHIP_MODE0
CHIP_MODE1
CHIP_MODE2
CHIP_MODE3
JTAG
JTAG_RESET
JTAG_CLOCK
JTAG_DI
JTAG_DO
JTAG_MODE
ARM Sub-system Signals
ARM_GPIO0
ARM_GPIO1
ARM_GPIO2
ARM_GPIO3
pdisdgz
pdidgz
pdidgz
pdidgz
pdidgz
pdudgz
pdisdgz
pdudgz
pdo02cdg
pdudgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
input Embedded board reset
E10
input Bypass the internal PLL and use PLL_BYPASS_CLK A9
input PLL bypass clock input
A10
N/A Analog 3.3 volt
D2
N/A Analog ground
D1
N/A 3.3 volt power for ESD Diodes
E3
N/A 3.3 volt power for ESD Diodes
A3
N/A 1.8 volt digital power for PLL
F3
N/A 1.8 volt digital ground for PLL
E2
input Bypass the TCXO and use the TCXO_BYPASS_CLK B10
input TCXO bypass clock
A11
input Bypass the XTAL oscillator and use the
D11
XTAL_BYPASS_CLK
input XTAL bypass clock
C12
output Enable the TCXO
B9
analog 32 kHz crystal (NOTE: Must be placed next to
B12
PVDD1DGZ.)
analog 32 kHz crystal
B11
Input Chip Reset
D10
Input Chip Mode Select
G3
Input Chip Mode Select
H2
Input Chip Mode Select
H1
Input Chip Mode Select
H3
Input Tap reset
L7
input Tap clock
L8
input Tap data in
M8
output Tap data out
K8
input Tap Mode
K9
bi-dir General Purpose I/O
M2
bi-dir General Purpose I/O
L3
bi-dir General Purpose I/O
K4
bi-dir General Purpose I/O
L4
LP1071 Advance Information, Rev. 0.5
18
Freescale Semiconductor
PRELIMINARY