LP1071 Datasheet, PDF (2/32 Pages) Freescale Semiconductor, Inc – 802.11a/b/g Baseband System

Introduction
terminal manufacturers can tune the chip performance to get the exact balance they opt for when it comes
to power consumption and performance.
1.2 General Description
The high-performance LP1071 baseband processor integrates the IEEE 802.11a/b/g PHY and full MAC
functionality with the industry’s smallest package and the lowest power consumption compared to any
baseband processor in the market.
The LP1071 was designed to target embedded devices and small form factor SDIO WLAN devices. Its
support for SDIO host interface combined with its ultra low power consumption and small size make it the
optimal solution for mobile devices. It has been designed with a generic RF interface that lets it interface
with virtually any RF components in the market. It has been fully tested to interface with RF solutions from
Maxim and Airoha, thus providing terminal manufacturers with added flexibility in selecting the most
appropriate RF parts based on their application and form factor.
The LP1071’s integrated ADC and DAC reduce the terminal manufacturers' bill of material and overall
system cost. The integrated internal memory eliminates the need for external MAC memory, further
reducing cost and saving valuable board space for small form factor devices.
The LP1071 also provides the highest level of WLAN security by fully supporting WPA and AES.
1.3 Feature Highlights
• Full compliance with 802.11a/b/g
• Ultra low power consumption, maximizing battery life and minimizing heat dissipation
• Ultra small package: 9.0 x 9.0 x 1.0 (max) mm
• Fully embedded ARM7TDMI® microprocessor for no load on the host processor, leading to
maximum flexibility in supporting different host platforms
• Implementations of 802.11e Draft, for support of Quality of Service (QoS) real-time applications
• 802.11i support, including WPA and AES, for enhanced security
• Automatic power management to reduce power consumption
• On-chip ADC and DAC to reduce system BOM and save on board area
• On-Chip PLL for clock generation
• On-chip ROM/RAM eliminating the need for external MAC memory
• Direct memory access (DMA) to reduce CPU utilization
• High throughput achieved using DMA
• Support of SDIO host interface
• Serial EEPROM interface for initialization and device booting
• Eight General Purpose I/O (GPIO) pins for added flexibility
• UART interface to support diagnostic tools and general data transfer
• JTAG Interface for testing and debugging
• Hardware engines for WEP, TKIP and AES support for less processor load
LP1071 Advance Information, Rev. 0.5
2
Freescale Semiconductor
PRELIMINARY