33894 Datasheet, PDF (4/28 Pages) Freescale Semiconductor, Inc – Quad High-Side Switch

PIN CONNECTIONS
Table 1. 33894 Pin Definitions (continued)
Functional descriptions of many of these pins can be found in Functional Description on page 16.
Pin Number Pin Name
Formal Name
Definition
10
CS
Chip Select
This input pin is connected to a chip select output of a master MCU. The MCU
(Active Low)
determines which device is addressed (selected) to receive data by pulling the CS pin
of the selected device logic LOW, thereby enabling SPI communication with the device.
Other unselected devices on the serial link having their CS pins pulled up logic HIGH
disregard the SPI communication data sent. This pin has an active internal pullup
current source and requires CMOS logic levels.
11
SCLK
Serial Clock
This input pin is connected to the MCU providing the required bit shift clock for SPI
communication. It transitions one time per bit transferred at an operating frequency,
f_SPI, defined by the communication interface. The 50 percent duty cycle CMOS level
serial clock signal is idle between command transfers. The signal is used to shift data
into and out of the device. This pin has an active internal pulldown current source.
12
SI
Serial Input
This pin is a command data input pin connected to the SPI Serial Data Output of the
microcontroller (MCU) or to the SO pin of the previous device of a daisy-chain of
devices. The input requires CMOS logic level signals and incorporates an internal
active pulldown. Device control is facilitated by the input's receiving the MSB first of a
serial 8-bit control command. The MCU ensures data is available upon the falling edge
of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit
command into the internal command shift register. This pin has an active internal
pulldown current source.
13
VDD
Digital Drain Voltage This pin is an external voltage input pin used to supply power to the SPI circuit. In the
(Power)
event V_DD is lost, an internal supply provides power to a portion of the logic, ensuring
limited functionality of the device.
14, 17, 23
GND
Ground
These pins are the ground for the logic and analog circuitry of the device.
15
VPWR Positive Power Supply This pin connects to the positive power supply and is the source of operational power
for the device. The V_PWR contact is the backside surface mount tab of the package.
16
SO
Serial Output
This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin
of the next device of a daisy-chain of devices. This output will remain tri-stated (high-
impedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only
active when the CS pin of the device is asserted logic LOW. The generated SO output
signals are CMOS logic levels. SO output data is available on the falling edge of SCLK
and transitions immediately on the rising edge of SCLK.
18
HS3
High-Side Outputs Protected 35 mΩ high-side power output pins to the load.
19
HS1
21
HS0
22
HS2
24
FSI
Fail-Safe Input
The value of the resistance connected between this pin and ground determines the
state of the outputs after a Watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is ON. If the FSI pin is left to
float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the Fail-
Safe state. When the FSI pin is connected to GND, the Watchdog circuit and Fail-Safe
operation are disabled. This pin incorporates an active internal pullup current source.
33894
4
Analog Integrated Circuit Device Data
Freescale Semiconductor