33894 Datasheet, PDF (17/28 Pages) Freescale Semiconductor, Inc – Quad High-Side Switch

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33894 has four operating modes: Sleep, Normal,
Fault, and Fail-Safe. Table 5 summarizes details contained in
succeeding paragraphs.
Table 5. Fail-Safe Operation and Transitions
to Other 33894 Modes
Mode
Sleep
FS
WAK
E
RST WDTO
Comments
x
0
0
x Device is in Sleep mode. All
outputs are OFF
Normal 1
x
1 No Normal mode. Watchdog is
active if enabled.
0
1
1
Device is currently in Fault
Fault 0
1
0 No ^{mode. The faulted output(s)}
is (are) OFF.
0
x
1
1
0
1
Watchdog has timed out
1
1
1
1
1
0
and the device is in Fail-
Safe mode. The outputs are
as configured with the RFS
Fail-
Yes _{resistor connected to FSI.}
Safe
RST and WAKE must be
transitioned to logic [0]
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied
the FSI pin to ground.
x = Don’t care.
SLEEP MODE
The default mode of the 33894 is the Sleep mode. This is
the state of the device after first applying battery voltage
(V_PWR) prior to any I/O transitions. This is also the state of the
device when the WAKE and RST are both logic [0]. In the
Sleep mode, the output and all unused internal circuitry, such
as the internal 5.0 V regulator, are OFF to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to logic [0]. The 33894 will transition to the
Normal or Fail-Safe operating modes based on the WAKE
and RST inputs as defined in Table 5.
NORMAL MODE
The 33894 is in Normal mode when:
• V_PWR is within the normal voltage range.
• RST pin is logic [1].
• No fault has occurred.
FAIL-SAFE MODE
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or the RST input pin
transitions from logic [0] to logic [1]. The WAKE input is
capable of being pulled up to V_PWR with a series of limiting
resistance limiting the internal clamp current according to the
specification.
The Watchdog timeout is a multiple of an internal oscillator
and is specified in the Table 14, page 22. As long as the WD
bit (D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), based on the
programmed value of the WDR, the device will operate
normally. If an internal watchdog timeout occurs before the
WD bit, the device will revert to a Fail-Safe mode until the
device is reinitialized.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 6).
Table 6. Output State During Fail-Safe Mode
RFS (kΩ)
0
6.0
15
High-Side State
Fail-Safe Mode Disabled
All HS OFF
HS0 ON
HS1 : HS3 OFF
30
HS0 and HS2 ON
HS1 and HS3 OFF
In the Fail-Safe mode, the SPI register content is retained
except for overcurrent high and low detection levels and
timing, which are reset to their default value (SOCL, SOCH,
and OCTL). Then the watchdog, overvoltage,
overtemperature, and overcurrent circuitry (with default
value) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST pins
from logic [1] to logic [0] or forcing the FSI pin to logic [0].
Table 5 summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
If the FSI pin is tied to GND, the Watchdog fail-safe
operation is disabled.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33894
17