S12FTS128KV1 Datasheet, PDF (37/46 Pages) Freescale Semiconductor, Inc – 128k byte Flash (Non-Volatile) Memory

Freescale Semiconductor, In_Blc_oc._{k Guide — FTS128K V01.03}
8. Writing a second command to the FCMD register before executing the previously written
command.
9. Writing an invalid user command to the FCMD register in user mode.
10. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the command
register, FCMD.
11. The part enters STOP mode and a program or erase command is in progress. The command is
aborted and any pending command is killed.
12. When security is enabled, a command other than Mass-Erase originating from a non-secure
memory or from the Background Debug Mode is written to FCMD.
13. A “0” is written to the CBEIF bit in the FSTAT register.
The ACCERR flag will not be set if any Flash register is read during the command sequence.
If the Flash array is read during execution of an algorithm (i.e. CCIF bit in the FSTAT register is low) the
read will return non valid data and the ACCERR flag will not be set
If an ACCERR flag is set in either of the FSTAT registers the Command State Machine is locked. It is not
possible to launch another command on either block until the ACCERR flag is cleared.
The PVIOL flag will be set during the command write sequence after the word write to the Flash address
space if any of the following illegal operations are performed, causing the command sequence to
immediately abort:
1. Writing a Flash address to program in a protected area of the Flash.
2. Writing a Flash address to erase in a protected area of the Flash.
3. Writing the mass erase command to FCMD while any protection is enabled. See Protection register
description in 3.3.5.
If a PVIOL flag is set in either of the FSTAT registers the Command State Machine is locked. It is not
possible to launch another command on either block until the PVIOL flag is cleared.
4.2 Wait Mode
When the MCU enters WAIT mode and if any command is active (CCIF=0), that command and any
pending command will be completed.
The FTS256K module can recover the part from WAIT if the interrupts are enabled (see Section 6).
4.3 Stop Mode
If a command is active (CCIF = 0) when the MCU enters the STOP mode, the command will be aborted,
and the data being programmed or erased is lost. The high voltage circuitry to the flash will be switched
off when entering STOP mode. CCIF and ACCERR flags will be set. If commands are active in both
blocks when STOP occurs, then all the corresponding CCIF and ACCERR flags will be set. Upon exit
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