S12FTS128KV1 Datasheet, PDF (23/46 Pages) Freescale Semiconductor, Inc – 128k byte Flash (Non-Volatile) Memory

Freescale Semiconductor, In_Blc_oc._{k Guide — FTS128K V01.03}
In user modes, all bits in the FTSTMOD register read zero and are not writable. The WRALL bit is
writable only in special modes. The purpose of this bit is to launch a command on all blocks in parallel.
This can be useful for mass erase and blank check operations. All other bits in this register must be written
to zero at all times.
WRALL —Write to all register banks.
If this bit is set, all banked registers sharing the same address will be written simultaneously.
1 = Write to all register banks.
0 = Write only to the bank selected via BKSEL.
3.3.4 FCNFG — Flash Configuration Register
The FCNFG register enables the Flash interrupts, gates the security backdoor writes and selects the register
bank to be operated on. This register is not banked.
Register address BASE + $103
7
6
5
4
3
2
1
0
R
CBEIE CCIE KEYACC
0
0
0
0
BKSEL
W
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-5 Flash Configuration Register (FCNFG)
CBEIE, CCIE, KEYACC and BKSEL are readable and writable. Bits 4-1 read zero and are not writable.
CBEIE — Command Buffer Empty Interrupt Enable.
The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash.
1 = An interrupt will be requested whenever the CBEIF flag, Figure 3-7, is set.
0 = Command Buffer Empty interrupts disabled.
CCIE — Command Complete Interrupt Enable.
The CCIE bit enables the interrupts in case of all commands being completed in the Flash.
1 = An interrupt will be requested whenever the CCIF, Figure 3-7, flag is set.
0 = Command Complete interrupts disabled.
KEYACC — Enable Security Key Writing.
1 = Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array
return invalid data.
0 = Flash writes are interpreted as the start of a program or erase sequence.
BKSEL — Register Bank Select
This bit is used to select one of the two register banks. The register bank associated with Flash 0 is the
default out of reset. The bank selection is according to Table 3-5.
23
For More Information On This Product,
Go to: www.freescale.com